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    • Apply as Trainer
  • Courses
    • For Freshers
      • Physical Design
      • Design For Test
      • ASIC Verification
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      • RTL Coding and FPGA Design
      • Embedded Systems Training
      • Analog Circuit Design
    • For Working Professionals
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      • Design For Test-Part Time
      • ASIC Verification-Part Time
      • Analog Layout Design-Part Time
      • RTL Coding and FPGA Design-Part Time
      • Analog Circuit Design
      • FINFET Layout Design Training
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ASIC Verification-Part Time

Trainer
Mr.Rajiv
Category:
For Working Professionals/
₹80,000.00
ASIC Verification-Part Time

Register Now
20 Students
Duration: 20 Weeks
Takshila VLSI Certificate

ASIC Verification Training / RTL Verification Training

COURSE DESCRIPTION

Mainly focused on enhancing the Design Verification skills needed by industry. The curriculum is designed to include the latest methodologies being adopted by industry. By end of the course you will have hands on experience in design and verification with Verilog, system Verilog (SV) in UVM methodology.

Takshila VLSI is one of the renowned Verilog and UVM training institute in Bangalore.

Eligibility

  • B.E/B.Tech in ECE/EEE.
  • M.E/M.Tech/M.S in VLSI/Embedded Systems/Digital Electronics.

Course Features and Highlights

  • Understanding on ASIC/FPGA Design Flows.
  • Deep understanding of Advanced Digital Logic concepts and Designs Verification skills.
  • Strong hands on System Verilog and UVM for Design Verification.
  • Developing the Verification Plan, Functional Coverage closure, SVAs etc.
  • Regression flow automation.
  • 24×7 Lab Support with Lab practice handouts and course material delivery.
  • Industry standard project execution, Lab practice and theory sessions under the guidance of industry expert with 12+ years of experience.
  • Soft skills development, complete suite of job oriented ASIC Verification training with 100% placement assistance.

Verilog, RTL Design, RTL Verification and UVM Training Institute

COURSE CURRICULUM

Module 1 : Basics of Unix/Linux

Introduction to Unix/Linux OS Architecture  
UNIX Directory Structures and Unix Commands  
UNIX Shells  
LAB Exercises  

Module 2 : Advanced Digital Electronics and Digital Logic Designs

Revision of Digital Electronics  
Basics of CMOS Logic Design and Realization of Digital Circuits  
Advanced Arithmatic and Logic Designs  
Logic Design using ROM, PLA, PALs  
ASIC and FPGA Design Flows and Architectures  

Module 3 : Computer Architecture, Microprocessors and Micro Controllers

Revision of 8086 and 8051 Architectures and Instruction Set  
RISC and CISC Processor Architectures  
Programming (ASM)  
Introduction to Modern System Level Architectures  

Module 4 : Scripting Languages (Widely Used in Industry)

Basics of PERL and TCL  
Introduction to Process Automation using Perl Scripting  

Module 5 : EDA Tool Introduction

Logic Simulation Tools - Questa Sim  
Logic Synthesis Tools  

Module 6 : HDLs For Digital Logic Design and Verification

Introduction to HDLs  
HDL Flows  

Module 7 : Digital Logic Design and Verification using Verilog

Module 8 : Mini Project on Verilog

Module 9 : Introduction to Logic Synthesis

Module 10 : Introduction to Object Oriented Programming

Module 11 : Design Verification using System Verilog

Introduction to System Verilog
SV Data Types
Memories
Tasks and Functions
Interfaces
Clocking Blocks
Introduction to Object Oriented Programming
OOPs Basics
Inheritance and Polymorphism
Ramdomization
Constraints
Threads and Mailboxs
Types of Threads
Mailbox Methods
Semaphore
Virtual Interface
Introduction to Callbacks  
Functional Coverage
Covergroup
Coverpoints and Bins
Introduction to Assertions
Types of Assertions
Building in SVA
Types of Operators
Types of Methods

Module 12 : Mini Project on System Verilog

Module 13 : Introduction to Verification Methodologies

Module 14 : Design Verification using UVM

Introduction to UVM Methodology  
Testbench Architecture  
UVM Phases  
TLM Overview  
UVM Sequences and Sequencers  
Builiding a Scoreboard  
Building a Reusable Environments  

Module 15 : Mini Project on UVM

Module 16 : Introduction to ARM System Architecture

Module 17 : Introduction to Communication Bus Protocols

Module 18 : Developing Verification Plan, Test Plan, Functional Coverage Plan and Coverage Analysis

Module 19 : Gate Level Simulations

Module 20 : Soft Skill Development Programs

About Instructors

Mr.Rajiv
Mr. Rajiv comes with a 13+ years of rich experience in Design Verification in IP, Sub-System and SoC levels. Working experience in multiple protocols like PCIe, USB, SATA, DDR, Ethernet etc, and also he has working experience in both ASIC and FPGA design flows. We believe his solid knowledge on Digital and Advaced System Architectures adopted by industry helps the students to shape themselves as good VLSI engineers.

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20 Students
Duration: 20 Weeks
Takshila VLSI Certificate

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Course categories

  • For Freshers (7)
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Working hours

Monday 9:30 am - 6.30 pm
Tuesday 9:30 am - 6.30 pm
Wednesday 9:30 am - 6.30 pm
Thursday 9:30 am - 6.30 pm
Friday 9:30 am - 6.30 pm
Saturday 8:00 am - 6.30 pm
Sunday 8:00 am - 6.30 pm

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Takshila VLSI institute is among the top 10 VLSI training institutes in India. At Takshila, we understand the changing demands in the field of VLSI.
Our courses are designed to offer students hands-on experience in industry trends.

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