Postal Address:

Laxmi Sagar Layout,
Mahadevapura, Bengaluru,
Karnataka – 560048, India

Skype:

Chaitanya_TIVT

Web:

www.takshila-vlsi.com

About Mr. Chaitanya

Mr. Chaitanya comes with 10+ years of experience in RTL2GDSII implementation of IP’s, Sub-System’s and SoC’s. Hands on experience in RTL2GDSII flow on multiple complex blocks like PCIe, SATA, DDR_PHY, HBM_PHY, processor’s and also have experience on DFT design flows and Design Constraints development. Good experience on clock tree building strategies for Full-Chip and Static Timing Analysis and Timing Closure on Full-Chip designs. We believe his solid knowledge on Digital and Physical Design implementation adopted by industry helps the students to shape themselves as good VLSI engineers.

Expertise Areas:

Low power implementation and strategies
Mode specific Design constraints development
Clock Tree Building at Block and Full-Chip
Full-Chip Timing Analysis and Timing Closure
Logical Equivalence Check and Low power checks
SI/Cross_talk analysis

Technology Process Worked On:
Finfet Technologies: 7nm and 16nm
Nominal Technologies: 28nm, 40nm, 65nm, 90nm & 130nm.

IC Foundries Worked with: TSMC, UMC, GF

EDA tools known for Physical design : Genus/RTL_Compiler/DC, Conformal, Encounter/Innovus, QRC Extraction, PrimeTime/Tempus
Physical verification tools known: Redhawk/Voltus, Calibre DRC, Calibre LVS

Mr. Chaitanya comes with 10+ years of experience in RTL2GDSII implementation of IP’s, Sub-System’s and SoC’s. Hands on experience in RTL2GDSII flow on multiple complex blocks like PCIe, SATA, DDR_PHY, HBM_PHY, processor’s and also have experience on DFT design flows and Design Constraints development. Good experience on clock tree building strategies for Full-Chip and Static Timing Analysis and Timing Closure on Full-Chip designs. We believe his solid knowledge on Digital and Physical Design implementation adopted by industry helps the students to shape themselves as good VLSI engineers.