Postal Address:
No. 39/4, 2nd Floor, Kishan Arcade
Ferns City Road, Mahadevapura,
Bengaluru , Karnataka – 560048.
Phone:
Skype:
Siva_TIVT
Email:
Web:
www.takshila-vlsi.com
About Mr. Siva
Mr. Siva comes with 12+ years of experience VLSI Industry , with substantial experience in DFT and worked as a Lead Engineer in several product companies. He is passionate about teaching & sharing his knowledge and mentored entry/mid-level engineers throughout his career. We believe his solid knowledge on Digital and Physical Design implementation adopted by industry helps the students to shape themselves as good VLSI engineers.
Expertise Areas:
Low power implementation and strategies
Mode specific Design constraints development
Clock Tree Building at Block and Full-Chip
Full-Chip Timing Analysis and Timing Closure
Logical Equivalence Check and Low power checks
SI/Cross_talk analysis
Technology Process Worked On:
Finfet Technologies: 7nm and 16nm
Nominal Technologies: 28nm, 40nm, 65nm, 90nm & 130nm.
IC Foundries Worked with: TSMC, UMC, GF
EDA tools known for Physical design : Genus/RTL_Compiler/DC, Conformal, Encounter/Innovus, QRC Extraction, PrimeTime/Tempus
Physical verification tools known: Redhawk/Voltus, Calibre DRC, Calibre LVS
Mr. Siva comes with 12+ years of experience VLSI Industry , with substantial experience in DFT and worked as a Lead Engineer in several product companies. He is passionate about teaching & sharing his knowledge and mentored entry/mid-level engineers throughout his career. We believe his solid knowledge on Digital and Physical Design implementation adopted by industry helps the students to shape themselves as good VLSI engineers.