How to Choose a Project<\/h2>\n\n- Pick the area you want to work in. A verification project helps a verification application more than a random RTL one.<\/li>\n
- Start one level below your comfort zone and finish it fully. A complete small project beats an abandoned big one.<\/li>\n
- Choose projects where you can show measurable results, such as timing numbers, coverage percentages or bugs found.<\/li>\n
- Avoid copying a project from the internet without changes. Add your own feature or analysis so you can speak about it honestly.<\/li>\n<\/ul>\n
RTL Design Projects<\/h2>\nBeginner: UART Transmitter and Receiver<\/h3>\n
Objective:<\/strong> implement serial communication with a configurable baud rate.<\/p>\nBlock view:<\/strong> baud-rate generator, transmitter FSM with shift register, receiver FSM with sampling logic, and a top module with a simple FIFO buffer.<\/p>\nTools:<\/strong> Icarus Verilog or any simulator, plus GTKWave. Expected output:<\/strong> waveforms showing correct frames and a testbench that checks received data automatically.<\/p>\nBeginner: Synchronous FIFO<\/h3>\n
Objective:<\/strong> design a parameterizable FIFO with full and empty flags.<\/p>\nBlock view:<\/strong> memory array, write pointer, read pointer and status logic. Expected output:<\/strong> passing tests for overflow, underflow and simultaneous read and write.<\/p>\nIntermediate: Pipelined ALU or MAC Unit<\/h3>\n
Objective:<\/strong> build an arithmetic unit and improve its clock frequency using pipelining.<\/p>\nBlock view:<\/strong> operand registers, arithmetic stages and an output register. Tools:<\/strong> simulator and a synthesis tool. Expected output:<\/strong> a before-and-after table of maximum frequency and area.<\/p>\nAdvanced: Simple RISC-V Core<\/h3>\n
Objective:<\/strong> implement a small RISC-V subset with fetch, decode, execute, memory and write-back stages.<\/p>\nBlock view:<\/strong> program counter, instruction memory, register file, ALU, control unit, data memory and hazard handling. Expected output:<\/strong> running a small assembly program and documenting the pipeline behaviour.<\/p>\nVerification Projects<\/h2>\nBeginner: Layered Testbench for a FIFO or Memory<\/h3>\n
Objective:<\/strong> build a generator, driver, monitor and scoreboard in SystemVerilog.<\/p>\nExpected output:<\/strong> random tests with automatic checking and a short report listing the scenarios covered.<\/p>\nIntermediate: UVM Environment for an APB Slave<\/h3>\n
Objective:<\/strong> verify a register-based peripheral using UVM.<\/p>\nBlock view:<\/strong> APB agent, scoreboard, coverage collector, base sequence and random sequences. Tools:<\/strong> VCS, Xcelium or Questa. Expected output:<\/strong> functional coverage report, assertions for protocol rules and a list of inserted bugs your environment caught.<\/p>\nAdvanced: UVM Environment for AXI or a Memory Controller<\/h3>\n
Objective:<\/strong> verify a more complex protocol with multiple agents, virtual sequences and a reference model.<\/p>\nExpected output:<\/strong> regression results across many seeds, closed coverage and a written verification plan.<\/p>\nPhysical Design Projects<\/h2>\n
![\"Physical](\"https:\/\/www.takshila-vlsi.com\/blog\/wp-content\/uploads\/2026\/11\/Physical-Design-Projects.png\")
<\/p>\n
Beginner: Place and Route a Small Block<\/h3>\n
Objective:<\/strong> take a small design, such as a counter or UART, through the complete flow.<\/p>\nStages:<\/strong> floorplan, power grid, placement, clock tree, routing and basic checks. Expected output:<\/strong> screenshots of each stage, a final timing summary and a clean DRC report.<\/p>\nIntermediate: Timing Closure Exercise<\/h3>\n
Objective:<\/strong> start with a block that fails setup or hold and bring it to clean timing.<\/p>\nExpected output:<\/strong> a log of each fix you tried, the slack improvement and your reasoning.<\/p>\nAdvanced: Hierarchical Design with Macros<\/h3>\n
Objective:<\/strong> implement a design that includes memory macros, with careful floorplanning, power planning and congestion management.<\/p>\nExpected output:<\/strong> a final layout with IR-drop analysis and a comparison of at least two floorplan strategies.<\/p>\nDFT Projects<\/h2>\nBeginner: Scan Insertion on a Small Design<\/h3>\n
Objective:<\/strong> convert a design into a scan-ready one and verify the scan chain.<\/p>\nExpected output:<\/strong> scan chain report, shift and capture simulation and design rule check results.<\/p>\nIntermediate: ATPG and Coverage Analysis<\/h3>\n
Objective:<\/strong> generate stuck-at and transition patterns, and analyse untestable faults.<\/p>\nExpected output:<\/strong> coverage numbers, pattern count and a short explanation of why specific faults remain undetected.<\/p>\nAdvanced: Memory BIST and Boundary Scan Integration<\/h3>\n
Objective:<\/strong> add memory BIST and a JTAG-style test access port to a design.<\/p>\nExpected output:<\/strong> working BIST simulation with injected memory faults and a boundary scan test sequence.<\/p>\nQuick Reference Table<\/h2>\n
\n\n\nArea<\/strong><\/td>\nBeginner<\/strong><\/td>\nIntermediate<\/strong><\/td>\nAdvanced<\/strong><\/td>\n<\/tr>\n<\/thead>\n\n\nRTL design<\/td>\n UART, FIFO<\/td>\n Pipelined ALU, SPI controller<\/td>\n RISC-V core<\/td>\n<\/tr>\n \nVerification<\/td>\n Layered testbench<\/td>\n UVM for APB slave<\/td>\n UVM for AXI or memory controller<\/td>\n<\/tr>\n \nPhysical design<\/td>\n Small block full flow<\/td>\n Timing closure<\/td>\n Hierarchical design with macros<\/td>\n<\/tr>\n \nDFT<\/td>\n Scan insertion<\/td>\n ATPG and coverage<\/td>\n Memory BIST and JTAG<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n <\/p>\n
Presenting Your Project Like a Professional<\/h2>\n\n- Write a one-page summary<\/strong> covering the problem, your approach, tools and results.<\/li>\n
- Use a block diagram.<\/strong> One clear picture explains more than three paragraphs.<\/li>\n
- Show numbers.<\/strong> Frequency, area, coverage, slack, bugs found and pattern count all make your claim concrete.<\/li>\n
- Keep a clean repository<\/strong> with a README, source files, scripts and results.<\/li>\n
- Be honest about limitations<\/strong> and mention what you would improve next.<\/li>\n
- Prepare a two-minute spoken version<\/strong> for interviews.<\/li>\n<\/ol>\n
Common Project Mistakes<\/h2>\n
RTL Design Projects<\/h2>\nBeginner: UART Transmitter and Receiver<\/h3>\n
Objective:<\/strong> implement serial communication with a configurable baud rate.<\/p>\n Block view:<\/strong> baud-rate generator, transmitter FSM with shift register, receiver FSM with sampling logic, and a top module with a simple FIFO buffer.<\/p>\n Tools:<\/strong> Icarus Verilog or any simulator, plus GTKWave. Expected output:<\/strong> waveforms showing correct frames and a testbench that checks received data automatically.<\/p>\n Objective:<\/strong> design a parameterizable FIFO with full and empty flags.<\/p>\n Block view:<\/strong> memory array, write pointer, read pointer and status logic. Expected output:<\/strong> passing tests for overflow, underflow and simultaneous read and write.<\/p>\n Objective:<\/strong> build an arithmetic unit and improve its clock frequency using pipelining.<\/p>\n Block view:<\/strong> operand registers, arithmetic stages and an output register. Tools:<\/strong> simulator and a synthesis tool. Expected output:<\/strong> a before-and-after table of maximum frequency and area.<\/p>\n Objective:<\/strong> implement a small RISC-V subset with fetch, decode, execute, memory and write-back stages.<\/p>\n Block view:<\/strong> program counter, instruction memory, register file, ALU, control unit, data memory and hazard handling. Expected output:<\/strong> running a small assembly program and documenting the pipeline behaviour.<\/p>\n Objective:<\/strong> build a generator, driver, monitor and scoreboard in SystemVerilog.<\/p>\n Expected output:<\/strong> random tests with automatic checking and a short report listing the scenarios covered.<\/p>\n Objective:<\/strong> verify a register-based peripheral using UVM.<\/p>\n Block view:<\/strong> APB agent, scoreboard, coverage collector, base sequence and random sequences. Tools:<\/strong> VCS, Xcelium or Questa. Expected output:<\/strong> functional coverage report, assertions for protocol rules and a list of inserted bugs your environment caught.<\/p>\n Objective:<\/strong> verify a more complex protocol with multiple agents, virtual sequences and a reference model.<\/p>\n Expected output:<\/strong> regression results across many seeds, closed coverage and a written verification plan.<\/p>\n Objective:<\/strong> take a small design, such as a counter or UART, through the complete flow.<\/p>\n Stages:<\/strong> floorplan, power grid, placement, clock tree, routing and basic checks. Expected output:<\/strong> screenshots of each stage, a final timing summary and a clean DRC report.<\/p>\n Objective:<\/strong> start with a block that fails setup or hold and bring it to clean timing.<\/p>\n Expected output:<\/strong> a log of each fix you tried, the slack improvement and your reasoning.<\/p>\n Objective:<\/strong> implement a design that includes memory macros, with careful floorplanning, power planning and congestion management.<\/p>\n Expected output:<\/strong> a final layout with IR-drop analysis and a comparison of at least two floorplan strategies.<\/p>\n Objective:<\/strong> convert a design into a scan-ready one and verify the scan chain.<\/p>\n Expected output:<\/strong> scan chain report, shift and capture simulation and design rule check results.<\/p>\n Objective:<\/strong> generate stuck-at and transition patterns, and analyse untestable faults.<\/p>\n Expected output:<\/strong> coverage numbers, pattern count and a short explanation of why specific faults remain undetected.<\/p>\n Objective:<\/strong> add memory BIST and a JTAG-style test access port to a design.<\/p>\n Expected output:<\/strong> working BIST simulation with injected memory faults and a boundary scan test sequence.<\/p>\n <\/p>\nBeginner: Synchronous FIFO<\/h3>\n
Intermediate: Pipelined ALU or MAC Unit<\/h3>\n
Advanced: Simple RISC-V Core<\/h3>\n
Verification Projects<\/h2>\n
Beginner: Layered Testbench for a FIFO or Memory<\/h3>\n
Intermediate: UVM Environment for an APB Slave<\/h3>\n
Advanced: UVM Environment for AXI or a Memory Controller<\/h3>\n
Physical Design Projects<\/h2>\n
<\/p>\nBeginner: Place and Route a Small Block<\/h3>\n
Intermediate: Timing Closure Exercise<\/h3>\n
Advanced: Hierarchical Design with Macros<\/h3>\n
DFT Projects<\/h2>\n
Beginner: Scan Insertion on a Small Design<\/h3>\n
Intermediate: ATPG and Coverage Analysis<\/h3>\n
Advanced: Memory BIST and Boundary Scan Integration<\/h3>\n
Quick Reference Table<\/h2>\n
\n\n
\n Area<\/strong><\/td>\n Beginner<\/strong><\/td>\n Intermediate<\/strong><\/td>\n Advanced<\/strong><\/td>\n<\/tr>\n<\/thead>\n\n \n RTL design<\/td>\n UART, FIFO<\/td>\n Pipelined ALU, SPI controller<\/td>\n RISC-V core<\/td>\n<\/tr>\n \n Verification<\/td>\n Layered testbench<\/td>\n UVM for APB slave<\/td>\n UVM for AXI or memory controller<\/td>\n<\/tr>\n \n Physical design<\/td>\n Small block full flow<\/td>\n Timing closure<\/td>\n Hierarchical design with macros<\/td>\n<\/tr>\n \n DFT<\/td>\n Scan insertion<\/td>\n ATPG and coverage<\/td>\n Memory BIST and JTAG<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n Presenting Your Project Like a Professional<\/h2>\n
\n
Common Project Mistakes<\/h2>\n