How VLSI Interviews Are Usually Structured<\/h2>\n\n- Screening round:<\/strong> a short call covering basics such as digital electronics and your resume.<\/li>\n
- Technical rounds:<\/strong> deep questions in your specialization, often with problems solved on paper or a whiteboard.<\/li>\n
- Project discussion:<\/strong> questions about your own work, where depth matters more than polish.<\/li>\n
- HR round:<\/strong> motivation, communication and fit.<\/li>\n<\/ol>\n
The first two stages share a common core, so start there.<\/p>\n
Core Topic 1: Digital Electronics<\/h2>\n
Nearly every interview, whatever the specialization, begins here. Be ready for:<\/p>\n
\n- Setup time, hold time and what happens when either is violated<\/li>\n
- Metastability and how synchronizers reduce its risk<\/li>\n
- Differences between latches and flip-flops<\/li>\n
- Designing a sequence detector with an FSM<\/li>\n
- Minimising logic with Boolean algebra and K-maps<\/li>\n
- Frequency dividers, including divide-by-odd-numbers with 50 percent duty cycle<\/li>\n
- FIFO depth calculation for different read and write rates<\/li>\n<\/ul>\n
Core Topic 2: Verilog and RTL Coding<\/h2>\n\n- Blocking versus non-blocking assignments, with an example of each<\/li>\n
- How an unintended latch gets inferred<\/li>\n
- Difference between wire and reg, and between always and assign<\/li>\n
- Synchronous versus asynchronous reset<\/li>\n
- Writing a synchronous FIFO, a clock divider or an edge detector on paper<\/li>\n
- Difference between a task and a function<\/li>\n<\/ul>\n
Interviewers often ask you to write short code live. Practise by hand, without a simulator, until your syntax is reliable.<\/p>\n
Core Topic 3: SystemVerilog and UVM (Verification Roles)<\/h2>\n\n- Difference between a class and a module, and a handle and an object<\/li>\n
- What is polymorphism, and why does UVM depend on it?<\/li>\n
- Mailbox, semaphore and event: when would you use each?<\/li>\n
- Constraints, randomization and how to debug a randomization failure<\/li>\n
- Functional coverage versus code coverage<\/li>\n
- UVM phases, factory and the configuration database<\/li>\n
- Sequence, sequencer and driver handshake<\/li>\n
- How would you verify a FIFO? Walk through your plan.<\/li>\n<\/ul>\n
Core Topic 4: Static Timing Analysis<\/h2>\n
STA matters for physical design and DFT roles, and is useful knowledge for RTL engineers as well.<\/p>\n
\n- How setup and hold slack are calculated<\/li>\n
- What causes a hold violation and ways to fix it<\/li>\n
- What is clock skew, and can it ever be helpful?<\/li>\n
- Meaning of multiple corners, on-chip variation and derating<\/li>\n
- False paths and multicycle paths: when do you declare them?<\/li>\n
- Clock gating checks and recovery and removal checks<\/li>\n<\/ul>\n
Core Topic 5: Physical Design<\/h2>\n\n- Steps from netlist to GDSII, in order<\/li>\n
- What goes into a good floorplan?<\/li>\n
- How do you handle congestion?<\/li>\n
- Clock tree synthesis goals and the meaning of skew and insertion delay<\/li>\n
- Difference between global and detailed routing<\/li>\n
- IR drop and electromigration, and how power planning addresses them<\/li>\n
- Antenna violations and their fixes<\/li>\n
- Crosstalk and its impact on timing<\/li>\n<\/ul>\n
Core Topic 6: Design for Testability<\/h2>\n\n- Why DFT is needed, and what scan insertion does<\/li>\n
- Working of a scan flip-flop in shift and capture modes<\/li>\n
- Stuck-at versus transition fault models<\/li>\n
- What fault coverage means and how to improve it<\/li>\n
- Purpose of a lockup latch<\/li>\n
- Memory BIST and boundary scan basics<\/li>\n<\/ul>\n
Specialization-Wise Focus<\/h2>\n
\n\n\nTarget role<\/strong><\/td>\nHighest priority topics<\/strong><\/td>\nSupporting topics<\/strong><\/td>\n<\/tr>\n<\/thead>\n\n\nRTL design<\/td>\n Verilog, FSM, digital logic, CDC<\/td>\n Synthesis, STA basics<\/td>\n<\/tr>\n \nVerification<\/td>\n SystemVerilog, UVM, coverage, debug<\/td>\n Digital design, protocols<\/td>\n<\/tr>\n \nPhysical design<\/td>\n STA, floorplan, CTS, routing<\/td>\n Scripting, power analysis<\/td>\n<\/tr>\n \nDFT<\/td>\n Scan, ATPG, fault models<\/td>\n STA, Verilog, BIST<\/td>\n<\/tr>\n \nAnalog layout<\/td>\n Matching, parasitics, DRC and LVS<\/td>\n CMOS and analog basics<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n![\"Four-Week](\"https:\/\/www.takshila-vlsi.com\/blog\/wp-content\/uploads\/2026\/11\/Four-Week-Preparation-Plan.png\")
<\/h2>\nA Four-Week Preparation Plan<\/h2>\n
\n\n\nWeek<\/strong><\/td>\nFocus<\/strong><\/td>\nDaily routine<\/strong><\/td>\n<\/tr>\n<\/thead>\n\n\n1<\/td>\n Digital electronics and Verilog basics<\/td>\n 60 minutes of theory, 30 minutes of coding or sketching<\/td>\n<\/tr>\n \n2<\/td>\n Core topics of your target specialization<\/td>\n Study one topic, then answer five questions aloud<\/td>\n<\/tr>\n \n3<\/td>\n Projects and STA or advanced topics<\/td>\n Rewrite your project explanation in simpler words<\/td>\n<\/tr>\n \n4<\/td>\n Mock interviews and weak areas<\/td>\n One mock interview and a review of mistakes<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n <\/p>\n
Prepare Your Projects Like Exam Topics<\/h2>\n
Interviewers will ask about anything on your resume, so every line must be defensible. For each project, be ready to answer:<\/p>\n
\n- What problem were you solving, and why?<\/li>\n
- What was your specific contribution?<\/li>\n
- What tools did you use?<\/li>\n
- What was the hardest bug or violation, and how did you fix it?<\/li>\n
- What would you change if you did it again?<\/li>\n<\/ul>\n
Mock Interview Exercises<\/h2>\n\n- Explain aloud:<\/strong> pick a topic such as setup and hold and explain it in two minutes to a friend who is not an engineer.<\/li>\n
- Whiteboard practice:<\/strong> solve a design problem with only paper and a pen.<\/li>\n
- Rapid-fire round:<\/strong> ask a partner to fire twenty short questions and answer each in one or two sentences.<\/li>\n
- Project grilling:<\/strong> have someone ask “why?” five times after each answer about your project.<\/li>\n
- Record yourself.<\/strong> Watching the recording reveals filler words and unclear explanations.<\/li>\n<\/ol>\n
Tips for the Day Itself<\/h2>\n
The first two stages share a common core, so start there.<\/p>\n
Core Topic 1: Digital Electronics<\/h2>\n
Nearly every interview, whatever the specialization, begins here. Be ready for:<\/p>\n
- \n
- Setup time, hold time and what happens when either is violated<\/li>\n
- Metastability and how synchronizers reduce its risk<\/li>\n
- Differences between latches and flip-flops<\/li>\n
- Designing a sequence detector with an FSM<\/li>\n
- Minimising logic with Boolean algebra and K-maps<\/li>\n
- Frequency dividers, including divide-by-odd-numbers with 50 percent duty cycle<\/li>\n
- FIFO depth calculation for different read and write rates<\/li>\n<\/ul>\n
Core Topic 2: Verilog and RTL Coding<\/h2>\n
- \n
- Blocking versus non-blocking assignments, with an example of each<\/li>\n
- How an unintended latch gets inferred<\/li>\n
- Difference between wire and reg, and between always and assign<\/li>\n
- Synchronous versus asynchronous reset<\/li>\n
- Writing a synchronous FIFO, a clock divider or an edge detector on paper<\/li>\n
- Difference between a task and a function<\/li>\n<\/ul>\n
Interviewers often ask you to write short code live. Practise by hand, without a simulator, until your syntax is reliable.<\/p>\n
Core Topic 3: SystemVerilog and UVM (Verification Roles)<\/h2>\n
- \n
- Difference between a class and a module, and a handle and an object<\/li>\n
- What is polymorphism, and why does UVM depend on it?<\/li>\n
- Mailbox, semaphore and event: when would you use each?<\/li>\n
- Constraints, randomization and how to debug a randomization failure<\/li>\n
- Functional coverage versus code coverage<\/li>\n
- UVM phases, factory and the configuration database<\/li>\n
- Sequence, sequencer and driver handshake<\/li>\n
- How would you verify a FIFO? Walk through your plan.<\/li>\n<\/ul>\n
Core Topic 4: Static Timing Analysis<\/h2>\n
STA matters for physical design and DFT roles, and is useful knowledge for RTL engineers as well.<\/p>\n
- \n
- How setup and hold slack are calculated<\/li>\n
- What causes a hold violation and ways to fix it<\/li>\n
- What is clock skew, and can it ever be helpful?<\/li>\n
- Meaning of multiple corners, on-chip variation and derating<\/li>\n
- False paths and multicycle paths: when do you declare them?<\/li>\n
- Clock gating checks and recovery and removal checks<\/li>\n<\/ul>\n
Core Topic 5: Physical Design<\/h2>\n
- \n
- Steps from netlist to GDSII, in order<\/li>\n
- What goes into a good floorplan?<\/li>\n
- How do you handle congestion?<\/li>\n
- Clock tree synthesis goals and the meaning of skew and insertion delay<\/li>\n
- Difference between global and detailed routing<\/li>\n
- IR drop and electromigration, and how power planning addresses them<\/li>\n
- Antenna violations and their fixes<\/li>\n
- Crosstalk and its impact on timing<\/li>\n<\/ul>\n
Core Topic 6: Design for Testability<\/h2>\n
- \n
- Why DFT is needed, and what scan insertion does<\/li>\n
- Working of a scan flip-flop in shift and capture modes<\/li>\n
- Stuck-at versus transition fault models<\/li>\n
- What fault coverage means and how to improve it<\/li>\n
- Purpose of a lockup latch<\/li>\n
- Memory BIST and boundary scan basics<\/li>\n<\/ul>\n
Specialization-Wise Focus<\/h2>\n
\n\n
\n Target role<\/strong><\/td>\n Highest priority topics<\/strong><\/td>\n Supporting topics<\/strong><\/td>\n<\/tr>\n<\/thead>\n\n \n RTL design<\/td>\n Verilog, FSM, digital logic, CDC<\/td>\n Synthesis, STA basics<\/td>\n<\/tr>\n \n Verification<\/td>\n SystemVerilog, UVM, coverage, debug<\/td>\n Digital design, protocols<\/td>\n<\/tr>\n \n Physical design<\/td>\n STA, floorplan, CTS, routing<\/td>\n Scripting, power analysis<\/td>\n<\/tr>\n \n DFT<\/td>\n Scan, ATPG, fault models<\/td>\n STA, Verilog, BIST<\/td>\n<\/tr>\n \n Analog layout<\/td>\n Matching, parasitics, DRC and LVS<\/td>\n CMOS and analog basics<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n <\/h2>\nA Four-Week Preparation Plan<\/h2>\n
\n\n
\n Week<\/strong><\/td>\n Focus<\/strong><\/td>\n Daily routine<\/strong><\/td>\n<\/tr>\n<\/thead>\n\n \n 1<\/td>\n Digital electronics and Verilog basics<\/td>\n 60 minutes of theory, 30 minutes of coding or sketching<\/td>\n<\/tr>\n \n 2<\/td>\n Core topics of your target specialization<\/td>\n Study one topic, then answer five questions aloud<\/td>\n<\/tr>\n \n 3<\/td>\n Projects and STA or advanced topics<\/td>\n Rewrite your project explanation in simpler words<\/td>\n<\/tr>\n \n 4<\/td>\n Mock interviews and weak areas<\/td>\n One mock interview and a review of mistakes<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n <\/p>\n
Prepare Your Projects Like Exam Topics<\/h2>\n
Interviewers will ask about anything on your resume, so every line must be defensible. For each project, be ready to answer:<\/p>\n
- \n
- What problem were you solving, and why?<\/li>\n
- What was your specific contribution?<\/li>\n
- What tools did you use?<\/li>\n
- What was the hardest bug or violation, and how did you fix it?<\/li>\n
- What would you change if you did it again?<\/li>\n<\/ul>\n
Mock Interview Exercises<\/h2>\n
- \n
- Explain aloud:<\/strong> pick a topic such as setup and hold and explain it in two minutes to a friend who is not an engineer.<\/li>\n
- Whiteboard practice:<\/strong> solve a design problem with only paper and a pen.<\/li>\n
- Rapid-fire round:<\/strong> ask a partner to fire twenty short questions and answer each in one or two sentences.<\/li>\n
- Project grilling:<\/strong> have someone ask “why?” five times after each answer about your project.<\/li>\n
- Record yourself.<\/strong> Watching the recording reveals filler words and unclear explanations.<\/li>\n<\/ol>\n
Tips for the Day Itself<\/h2>\n
- Whiteboard practice:<\/strong> solve a design problem with only paper and a pen.<\/li>\n
- Explain aloud:<\/strong> pick a topic such as setup and hold and explain it in two minutes to a friend who is not an engineer.<\/li>\n