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  • Takshila
    • About Us
    • Vision
    • Why Join Us
    • Blog
    • Apply as Trainer
  • Courses
    • For Freshers
      • Physical Design
      • Design For Test
      • ASIC Verification
      • Analog Layout Design
      • RTL Coding and FPGA Design
      • Embedded Systems Training
      • Analog Circuit Design
    • For Working Professionals
      • Physical Design-Part Time
      • Design For Test-Part Time
      • ASIC Verification-Part Time
      • Analog Layout Design-Part Time
      • RTL Coding and FPGA Design-Part Time
      • Analog Circuit Design
      • FINFET Layout Design Training
      • UVM Training
      • PERL Scripting
    • Online Courses
      • Physical Design Online
      • ASIC Verification Online
      • Analog Layout Design Online
      • RTL Coding and FPGA Design Online
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      • UVM Training Online
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Physical Design Online

Trainer
Mr.Chaitanya
Category:
Online Courses/
₹75,000.00

Register Now
15 Students
Duration: 4 Months
Takshila VLSI Certificate

VLSI Online Chip Design Training & Online Physical Design Courses in Bangalore

COURSE DESCRIPTION

Online Physical Design Training course mainly focused on giving complete hands on experience to physical design and physical verification training flow with latest tools and full lab practice. By end of the course your will learn to work in Linux environment, understand complete physical design flow from partitioning, floor planning, power planning, timing analysis, clock tree synthesis, routing of a functional unit blocks to physical verification and sign-off checks.

It is extensive training for students in the field of electrical and electronics. Takshila VLSI ranks among the top 10 physical design training institutes in the Bangalore.

Industry Standard Online VLSI and Online DFT Training

Eligibility

  • B.E/B.Tech in ECE/EEE.
  • M.E/M.Tech/M.S in VLSI/Embedded Systems/Digital Electronics.

Course Highlights:

  • Hands-on exposure to physical design flow with industry standard EDA tools.
  • Deep understanding of various methodologies and technologies used.
  • 24×7 Lab Support with Lab practice handouts and course material delivery.
  • Industry standard project execution from RTL to gdsii training, Lab practice and theory sessions under the guidance of industry expert with 12+ years of experience.
  • Soft skills development, complete suite of job oriented physical design training with 100% placement assistance

Online Physical design training institute with placement

COURSE CURRICULUM

Module 1: Basics of Unix/Linux

Introduction and Working knowledge of UNIX/LINUX commands  
File handling skills in UNIX/LINUX  
Introduction to programming languages used in IC-Design  

Module 2: Basics of CMOS

MOSFET Operation, stick diagram, IC fabrication process  
Formation of Digital (NAND AND OR NOR etc) logic using CMOS  

Module 3: Design and Tech libraries

Characterization of Digital standard cells and Library file information  
Technology File information, LEF file information, QRC Techfile process  
Basics RTL coding and RTL language like Verilog, VHDL, SystemVerilog  

Module 4: Synthesis Part-1

Inputs and Outputs understanding  
Constraints development and understanding  
Optimization techniques (uniqify, preserve, flatten )  
DFT basics  

Module 5: Synthesis Part-2

Low power implementation techniques  
Sanity checks like checkDesign, lint report  
Derive environment features  
Generic, map, incremental  
Wireload model, PLE, Physical, Spatial  

Module 6: Logical Equivalence

Inputs and outputs understanding  
Intent and comparison understanding  

Module 7: Static Timing Analysis Part-1

Basic understanding of transition/slew, capacitance, leakage power, internal power, On-Chip-Variation (derate, AOCV, LVF)  
Library file difference NLDM, CCS, ECSM, LVF  
Timing concepts understanding like setup, hold, recovery, removal, pulse_width, clock gating check  

Module 8: Static Timing Analysis Part-2

PLL jitter understanding and uncertainty calculations  
IO budgetting  
Different Timing Modes understanding  
ECO generation  

Module 9: Physical Design

Floorplaning concepts and IO placement  
Power planning  
Placement strategies like region, fence, blockages, pading, bump, dont touch, filler gap  
DRV optimization, Buffer tree synthesis  
Clock tree synthesis and clock latency calculations  
Routing design and optimization  
Antenna  
ECO Timing closure and implementation cycle  

Module 10: Physical Design Verification

Design Rule Checks understanding and importance  
Layout Versus Schematic and difference with respect to LEC  
Electrical Rule Checks  
IR Drop analysis - Static and Dynamic  

Module 11: Industry standard Project Execution

Industry Standard Physical Design Live Project  

Module 12: Mock Interviews & Personality improvement

About Instructors

Mr.Chaitanya
Mr. Chaitanya comes with 12+ years of experience in RTL to GDSII implementation of IP's, Sub-System's and SoC's. Hands on experience in RTL2GDSII flow of multiple complex blocks like PCIe, SATA, DDR_PHY, HBM_PHY, processor's and also have experience on DFT design flows and Design Constraints development.

Register Now
15 Students
Duration: 4 Months
Takshila VLSI Certificate

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Course categories

  • For Freshers (7)
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Working hours

Monday 9:30 am - 6.30 pm
Tuesday 9:30 am - 6.30 pm
Wednesday 9:30 am - 6.30 pm
Thursday 9:30 am - 6.30 pm
Friday 9:30 am - 6.30 pm
Saturday 8:00 am - 6.30 pm
Sunday 8:00 am - 6.30 pm

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Takshila VLSI institute is among the top 10 VLSI training institutes in India. At Takshila, we understand the changing demands in the field of VLSI.
Our courses are designed to offer students hands-on experience in industry trends.

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