Physical Design Online

Trainer
Mr.Chaitanya
Category:
Online Courses/
₹75,000.00

Register Now
15 Students
Duration: 4 Months
Takshila VLSI Certificate

VLSI Online Chip Design Training & Online Physical Design Courses in Bangalore

COURSE DESCRIPTION

Online Physical Design Training course mainly focused on giving complete hands on experience to physical design and physical verification training flow with latest tools and full lab practice. By end of the course your will learn to work in Linux environment, understand complete physical design flow from partitioning, floor planning, power planning, timing analysis, clock tree synthesis, routing of a functional unit blocks to physical verification and sign-off checks.

It is extensive training for students in the field of electrical and electronics. Takshila VLSI ranks among the top 10 physical design training institutes in the Bangalore.

Industry Standard Online VLSI and Online DFT Training

Eligibility

  • B.E/B.Tech in ECE/EEE.
  • M.E/M.Tech/M.S in VLSI/Embedded Systems/Digital Electronics.

Course Highlights:

  • Hands-on exposure to physical design flow with industry standard EDA tools.
  • Deep understanding of various methodologies and technologies used.
  • 24×7 Lab Support with Lab practice handouts and course material delivery.
  • Industry standard project execution from RTL to gdsii training, Lab practice and theory sessions under the guidance of industry expert with 12+ years of experience.
  • Soft skills development, complete suite of job oriented physical design training with 100% placement assistance

Online Physical design training institute with placement

COURSE CURRICULUM

Module 1: Basics of Unix/Linux

Module 2: Basics of CMOS

Module 3: Design and Tech libraries

Module 4: Synthesis Part-1

Module 5: Synthesis Part-2

Module 6: Logical Equivalence

Module 7: Static Timing Analysis Part-1

Module 8: Static Timing Analysis Part-2

Module 9: Physical Design

Module 10: Physical Design Verification

Module 11: Industry standard Project Execution

Module 12: Mock Interviews & Personality improvement

About Instructors

Mr.Chaitanya
Mr. Chaitanya comes with 12+ years of experience in RTL to GDSII implementation of IP's, Sub-System's and SoC's. Hands on experience in RTL2GDSII flow of multiple complex blocks like PCIe, SATA, DDR_PHY, HBM_PHY, processor's and also have experience on DFT design flows and Design Constraints development.