ASIC Verification-Part Time

Trainer
Mr.Rajiv
Category:
For Working Professionals/
₹80,000.00
ASIC Verification-Part Time

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20 Students
Duration: 20 Weeks
Takshila VLSI Certificate

ASIC Verification Training / RTL Verification Training

COURSE DESCRIPTION

Mainly focused on enhancing the Design Verification skills needed by industry. The curriculum is designed to include the latest methodologies being adopted by industry. By end of the course you will have hands on experience in design and verification with Verilog, system Verilog (SV) in UVM methodology.

Takshila VLSI is one of the renowned Verilog and UVM training institute in Bangalore.

Eligibility

  • B.E/B.Tech in ECE/EEE.
  • M.E/M.Tech/M.S in VLSI/Embedded Systems/Digital Electronics.

Course Features and Highlights

  • Understanding on ASIC/FPGA Design Flows.
  • Deep understanding of Advanced Digital Logic concepts and Designs Verification skills.
  • Strong hands on System Verilog and UVM for Design Verification.
  • Developing the Verification Plan, Functional Coverage closure, SVAs etc.
  • Regression flow automation.
  • 24×7 Lab Support with Lab practice handouts and course material delivery.
  • Industry standard project execution, Lab practice and theory sessions under the guidance of industry expert with 12+ years of experience.
  • Soft skills development, complete suite of job oriented ASIC Verification training with 100% placement assistance.

Verilog, RTL Design, RTL Verification and UVM Training Institute

COURSE CURRICULUM

Module 1 : Basics of Unix/Linux

Module 2 : Advanced Digital Electronics and Digital Logic Designs

Module 3 : Computer Architecture, Microprocessors and Micro Controllers

Module 4 : Scripting Languages (Widely Used in Industry)

Module 5 : EDA Tool Introduction

Module 6 : HDLs For Digital Logic Design and Verification

Module 7 : Digital Logic Design and Verification using Verilog

Module 8 : Mini Project on Verilog

Module 9 : Introduction to Logic Synthesis

Module 10 : Introduction to Object Oriented Programming

Module 11 : Design Verification using System Verilog

SV Data Types
Memories
Tasks and Functions
Interfaces
Clocking Blocks
OOPs Basics
Inheritance and Polymorphism
Ramdomization
Constraints
Types of Threads
Mailbox Methods
Semaphore
Virtual Interface
Covergroup
Coverpoints and Bins
Types of Assertions
Building in SVA
Types of Operators
Types of Methods

Module 12 : Mini Project on System Verilog

Module 13 : Introduction to Verification Methodologies

Module 14 : Design Verification using UVM

Module 15 : Mini Project on UVM

Module 16 : Introduction to ARM System Architecture

Module 17 : Introduction to Communication Bus Protocols

Module 18 : Developing Verification Plan, Test Plan, Functional Coverage Plan and Coverage Analysis

Module 19 : Gate Level Simulations

Module 20 : Soft Skill Development Programs

About Instructors

Mr.Rajiv
Mr. Rajiv comes with a 13+ years of rich experience in Design Verification in IP, Sub-System and SoC levels. Working experience in multiple protocols like PCIe, USB, SATA, DDR, Ethernet etc, and also he has working experience in both ASIC and FPGA design flows. We believe his solid knowledge on Digital and Advaced System Architectures adopted by industry helps the students to shape themselves as good VLSI engineers.
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