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Physical Design-Part Time

Trainer
Mr.Chaitanya
Category:
For Working Professionals/
₹85,000.00
Physical Design-Part Time

Register Now
20 Students
Duration: 20 Weeks
Takshila VLSI Certificate

VLSI Chip Design Training & Physical Design Courses in Bangalore

COURSE DESCRIPTION

Physical Design part time course mainly focused on giving complete hands on experience to physical design and physical verification flow with latest tools and full lab practice. By end of the course your will learn to work in Linux environment, understand complete physical design flow from portioning, floor planning, power planning, timing analysis, clock tree synthesis, routing of a functional unit blocks to physical verification and sign-off checks.

Industry Standard VLSI and DFT Training

Eligibility

  • B.E/B.Tech in ECE/EEE.
  • M.E/M.Tech/M.S in VLSI/Embedded Systems/Digital Electronics.

Course Highlights:

  • Hands-on exposure to physical design flow with industry standard EDA tools.
  • Deep understanding of various methodologies and technologies used.
  • 24×7 Lab Support with Lab practice handouts and course material delivery.
  • Industry standard project execution, Lab practice and theory sessions under the guidance of industry expert with 12+ years of experience.
  • Soft skills development, complete suite of job oriented physical design training with 100% placement assistance

Physical design training institute with placement

COURSE CURRICULUM

Module 1: Basics of Unix/Linux

Introduction and Working knowledge of UNIX/LINUX commands  
File handling skills in UNIX/LINUX  
Introduction to programming languages used in IC-Design  

Module 2: Basics of CMOS

MOSFET Operation, stick diagram, IC fabrication process  
Formation of Digital (NAND AND OR NOR etc) logic using CMOS  

Module 3: Design and Tech libraries

Characterization of Digital standard cells and Library file information  
Technology File information, LEF file information, QRC Techfile process  
Basics RTL coding and RTL language like Verilog, VHDL, SystemVerilog  

Module 4: Synthesis Part-1

Inputs and Outputs understanding  
Constraints development and understanding  
Optimization techniques (uniqify, preserve, flatten )  
DFT basics  

Module 5: Synthesis Part-2

Low power implementation techniques  
Sanity checks like checkDesign, lint report  
Derive environment features  
Generic, map, incremental  
Wireload model, PLE, Physical, Spatial  

Module 6: Logical Equivalence

Inputs and outputs understanding  
Intent and comparison understanding  

Module 7: Static Timing Analysis Part-1

Basic understanding of transition/slew, capacitance, leakage power, internal power, On-Chip-Variation (derate, AOCV, LVF)  
Library file difference NLDM, CCS, ECSM, LVF  
Timing concepts understanding like setup, hold, recovery, removal, pulse_width, clock gating check  

Module 8: Static Timing Analysis Part-2

PLL jitter understanding and uncertainty calculations  
IO budgetting  
Different Timing Modes understanding  
ECO generation  

Module 9: Physical Design

Floorplaning concepts and IO placement  
Power planning  
Placement strategies like region, fence, blockages, pading, bump, dont touch, filler gap  
DRV optimization, Buffer tree synthesis  
Clock tree synthesis and clock latency calculations  
Routing design and optimization  
Antenna  
ECO Timing closure and implementation cycle  

Module 10: Physical Design Verification

Design Rule Checks understanding and importance  
Layout Versus Schematic and difference with respect to LEC  
Electrical Rule Checks  
IR Drop analysis - Static and Dynamic  

Module 11: Industry standard Project Execution

Industry Standard Physical Design Live Project  

Module 12: Mock Interviews & Personality improvement

Physical Design Demo Videos

Frequently Asked Questions

1. What is the focus of the Physical Design Part-Time course?

Our Physical Design Part-Time course is all about hands-on experience in VLSI physical design. You will dive into everything from floor planning to routing and physical verification using the latest industry tools. Perfect for professionals who want to level up their skills!

2. Who should consider taking this VLSI physical design part-time course?

This course is the best option for working professionals who belong to electronics and are looking to deepen their knowledge in VLSI physical design. If you are an engineer or want to master physical design, this is for you!

3. What can you expect to learn in the Physical Design Education provided?

In our Physical Design Education, you’ll gain a thorough understanding of physical design flow. Expect to learn about Linux environments, power planning, timing analysis, and much more. By the end, you’ll be well-versed in the entire physical design process!

4. How does the Physical Design Part-Time course fit into my busy schedule?

The course is designed to fit around your existing job. You’ll get flexible access to lab support and materials, making it easier to balance learning with your work commitments.

5. Who can join the course in the Physical Design Classes?

You have to come from an electrical or electronics background, such as a B.E, B.Tech in ECE or EEE, or an M.E, M.Tech, or M.S in VLSI and Embedded Systems. This background ensures that you are able to learn the advanced topics.

6. Brief description of Physical design course details?

We provide the best practical knowledge about the tools and techniques and concentrate on placing you in the best company. It covers everything from basics like Unix/Linux commands and CMOS operations to advanced topics.

7. How experienced are the instructors for the Physical Design Course?

Our instructors, like Mr. Chaitanya, bring over 12 years of hands-on experience in RTL to GDSII implementation. They have worked on complex blocks like PCIe and DDR_PHY so you will be learning from true experts in the field.

8. What practical skills will you learn from the Physical Design for Professionals course?

You will learn and get real practice with industry-standard EDA tools. You’ll learn how to manage floor planning, power planning, and routing—all crucial skills for a career in physical design.

About Instructors

Mr.Chaitanya
Mr. Chaitanya comes with 12+ years of experience in RTL to GDSII implementation of IP's, Sub-System's and SoC's. Hands on experience in RTL2GDSII flow of multiple complex blocks like PCIe, SATA, DDR_PHY, HBM_PHY, processor's and also have experience on DFT design flows and Design Constraints development.

Register Now
20 Students
Duration: 20 Weeks
Takshila VLSI Certificate

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  • For Freshers (7)
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Friday 9:30 am - 6.30 pm
Saturday 8:00 am - 6.30 pm
Sunday 8:00 am - 6.30 pm

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