Postal Address:
No. 39/4, 2nd Floor, Kishan Arcade
Ferns City Road, Mahadevapura,
Bengaluru , Karnataka – 560048.
Phone:
Skype:
Rajiv_TIVT
Email:
Web:
www.takshila-vlsi.com
About Mr. Rajiv
Mr. Rajiv comes with a 13+ years of rich experience in Design Verification in IP, Sub-System and SoC levels. Working experience in multiple protocols like PCIe, USB, SATA, DDR, Ethernet etc, and also he has working experience in both ASIC and FPGA design flows.
We believe his solid knowledge on Digital and Advaced System Architectures adopted by industry helps the students to shape themselves as good VLSI engineers.
Skills:
Verilog, VHDL,
System Verilog
UVM, OVM, VMM
PERL
Protocols Worked On:
PCIe, USB, SATA, DDR, Ethernet
AMBA Protocols
Tools:
ModelSim, VCS, IRUN
Quartus II (Altera FPGA Development Platform)
Mr. Rajiv comes with a 13+ years of rich experience in Design Verification in IP, Sub-System and SoC levels. Working experience in multiple protocols like PCIe, USB, SATA, DDR, Ethernet etc, and also he has working experience in both ASIC and FPGA design flows.
We believe his solid knowledge on Digital and Advaced System Architectures adopted by industry helps the students to shape themselves as good VLSI engineers.