Recruiters in the semiconductor industry see hundreds of resumes that list the same subjects and the same marks. What makes one stand out is a project the candidate can explain in detail: what problem it solved, which tools were used, what went wrong and how it was fixed.
This guide collects VLSI projects for ECE students across four areas: RTL design, verification, physical design and DFT. Each idea includes its objective, a block-level description, tools, expected outputs and a tip for presenting it.
How to Choose a Project
- Pick the area you want to work in. A verification project helps a verification application more than a random RTL one.
- Start one level below your comfort zone and finish it fully. A complete small project beats an abandoned big one.
- Choose projects where you can show measurable results, such as timing numbers, coverage percentages or bugs found.
- Avoid copying a project from the internet without changes. Add your own feature or analysis so you can speak about it honestly.
RTL Design Projects
Beginner: UART Transmitter and Receiver
Objective: implement serial communication with a configurable baud rate.
Block view: baud-rate generator, transmitter FSM with shift register, receiver FSM with sampling logic, and a top module with a simple FIFO buffer.
Tools: Icarus Verilog or any simulator, plus GTKWave. Expected output: waveforms showing correct frames and a testbench that checks received data automatically.
Beginner: Synchronous FIFO
Objective: design a parameterizable FIFO with full and empty flags.
Block view: memory array, write pointer, read pointer and status logic. Expected output: passing tests for overflow, underflow and simultaneous read and write.
Intermediate: Pipelined ALU or MAC Unit
Objective: build an arithmetic unit and improve its clock frequency using pipelining.
Block view: operand registers, arithmetic stages and an output register. Tools: simulator and a synthesis tool. Expected output: a before-and-after table of maximum frequency and area.
Advanced: Simple RISC-V Core
Objective: implement a small RISC-V subset with fetch, decode, execute, memory and write-back stages.
Block view: program counter, instruction memory, register file, ALU, control unit, data memory and hazard handling. Expected output: running a small assembly program and documenting the pipeline behaviour.
Verification Projects
Beginner: Layered Testbench for a FIFO or Memory
Objective: build a generator, driver, monitor and scoreboard in SystemVerilog.
Expected output: random tests with automatic checking and a short report listing the scenarios covered.
Intermediate: UVM Environment for an APB Slave
Objective: verify a register-based peripheral using UVM.
Block view: APB agent, scoreboard, coverage collector, base sequence and random sequences. Tools: VCS, Xcelium or Questa. Expected output: functional coverage report, assertions for protocol rules and a list of inserted bugs your environment caught.
Advanced: UVM Environment for AXI or a Memory Controller
Objective: verify a more complex protocol with multiple agents, virtual sequences and a reference model.
Expected output: regression results across many seeds, closed coverage and a written verification plan.
Physical Design Projects
Beginner: Place and Route a Small Block
Objective: take a small design, such as a counter or UART, through the complete flow.
Stages: floorplan, power grid, placement, clock tree, routing and basic checks. Expected output: screenshots of each stage, a final timing summary and a clean DRC report.
Intermediate: Timing Closure Exercise
Objective: start with a block that fails setup or hold and bring it to clean timing.
Expected output: a log of each fix you tried, the slack improvement and your reasoning.
Advanced: Hierarchical Design with Macros
Objective: implement a design that includes memory macros, with careful floorplanning, power planning and congestion management.
Expected output: a final layout with IR-drop analysis and a comparison of at least two floorplan strategies.
DFT Projects
Beginner: Scan Insertion on a Small Design
Objective: convert a design into a scan-ready one and verify the scan chain.
Expected output: scan chain report, shift and capture simulation and design rule check results.
Intermediate: ATPG and Coverage Analysis
Objective: generate stuck-at and transition patterns, and analyse untestable faults.
Expected output: coverage numbers, pattern count and a short explanation of why specific faults remain undetected.
Advanced: Memory BIST and Boundary Scan Integration
Objective: add memory BIST and a JTAG-style test access port to a design.
Expected output: working BIST simulation with injected memory faults and a boundary scan test sequence.
Quick Reference Table
| Area | Beginner | Intermediate | Advanced |
| RTL design | UART, FIFO | Pipelined ALU, SPI controller | RISC-V core |
| Verification | Layered testbench | UVM for APB slave | UVM for AXI or memory controller |
| Physical design | Small block full flow | Timing closure | Hierarchical design with macros |
| DFT | Scan insertion | ATPG and coverage | Memory BIST and JTAG |
Presenting Your Project Like a Professional
- Write a one-page summary covering the problem, your approach, tools and results.
- Use a block diagram. One clear picture explains more than three paragraphs.
- Show numbers. Frequency, area, coverage, slack, bugs found and pattern count all make your claim concrete.
- Keep a clean repository with a README, source files, scripts and results.
- Be honest about limitations and mention what you would improve next.
- Prepare a two-minute spoken version for interviews.
Common Project Mistakes
- Listing too many tiny projects instead of a few well-documented ones
- Not being able to explain design decisions
- Skipping testing and showing only a working waveform
- Using code you do not understand
Start Building Today
Choose one project from the area you care about and set a finish date. Even a modest project, completed and documented well, shows employers that you can learn, build and communicate.
For guided projects and expert feedback, explore the hands-on courses and project resources at Takshila Institute of VLSI Technologies
